1. Field of the Invention
The present invention relates to NAND flash memory using EEPROM, for example, and particularly relates to a semiconductor memory device capable of storing multi-valued data by using a flag cell.
2. Description of the Related Art
In NAND flash memory, multiple memory cells arranged in a column direction are connected in series to form each of memory strings, and each memory string is connected to a corresponding one of bit lines via a select gate. Each bit line is connected to a sense amplifier circuit configured to sense and latch write data and read data. All or half of the multiple cells arranged in a word line direction are simultaneously selected and a write operation or a read operation is performed in a lump for all or half of the multiple cells thus simultaneously selected. Multiple NAND cells arranged in the word line direction form a block and an erase operation is executed in units of the blocks. In the erase operation, a threshold voltage of each memory cell is set to a negative value. In the write operation, the threshold voltage is raised by injecting electrons into the memory cell.
In the NAND cells, there is a case where data is stored separately in a lower page and an upper page in several operations to store multi-valued data. At this time, a flag cell is used in some cases to determine whether data is written in the upper page.